A 72 MHz processor does not mean 72 MHz flash memory, and it showed in our performance tests.
- 72 MHz = 14.15 mA (196.5 uA / MHz)
- 36 MHz = 8.24 mA (228.9 uA / MHz)
- 24.5 MHz = 5.48 mA (223.7 uA / MHz)
- 115.8 us period for 25-sample data stored in RAM @ 72 MHz (356 cycles per sample)
- 316.2 us period for 64-sample data stored in XRAM @ 72 MHz (380 clock cycles per sample)
- 600.5 us period @ 36 MHz (100 kHz, 360 clock cycles per sample)
- 810.1 us period @ 24.5 MHz (74 kHz, 330 clock cycles per sample)
245 clock cycles when using #define statements instead of const int16_t @ 24.5 MHz
222 cycles when not using xdata
246 cycles when not using xdata @ 72 MHz = 293 kHz biquad frequency
272 cycles when using xdata @ 72 MHz = 265 kHz biquad frequency
What they don’t tell you:
- UART 0 and SMBus (I2c) peripherals have no internal baud-rate generator, so you’ll have to kill a timer or two to handle this.
- We’ve had problems with all the C2 debuggers crapping out with certain USB hubs and USB controllers.
- Silicon Labs essentially waved the white flag and switched over to a paged system (a la Microchip PIC) for SFRs on their higher-end parts. In other words, SPIDAT and SMBDAT both have the same SFR address (0x38); they’re just on different pages, which requires you to add in an additional set of instructions to switch pages when necessary.