Infineon XMC1100

With no caching mechanism on the XMC1100, the bit-wiggle clock-cycle count test continued increasing as clock speed was brought up. At 32 MHz, it takes 9 clock cycles — to execute two instructions that execute on the core in 5 cycles.

Performance

GPIO toggling takes

Two instructions: store (2 cycles), branch (3) cycles. But somehow adds up to 8 cycles?

Biquad

Running out of flash, the XMC1100 brings in rather unimpressive numbers when compared to other ARM processors in the round-up; the lack of a flash caching mechanism penalized this 32 MHz core so badly that it performed at less than half the speed of the 48 MHz processors, making it look more like a 24 MHz chip. Drawing 4.26 mA put it toward the bad side of ARM competitors.

However, as I’ve mentioned before, this microcontroller’s memory configuration is backwards: it has 16 K of RAM and 8 K of flash. Simply decorate your main() function with:

__attribute__ ((section (".ram_code")))

and reap the rewards: 27 clocks per sample (the fastest in our round-up), and 2.90 mA active current (the lowest in our round up). The XMC1100 just went from a below-average student to the leader in the pack, with an impressive 8.03 nJ/sample (53 times more efficient than the AVR).